In the prior art, integrated circuit memory devices have been developed which store data for indefinite periods of time in the absence of electrical power being applied thereto and which also have the capability of selectively changing or programming the data stored therein. Of particular interest herein is a nonvolatile memory cell which utilizes a floating gate as the nonvolatile element. See e.g., U.S. Pat. No. 4,314,265 which discloses a four polysilicon layer, floating gate nonvolatile memory cell, and U.S. Pat. No. 4,274,012 which discloses a three polysilicon layer, floating gate nonvolatile memory cell with substrate coupling. Either of these nonvolatile memory cells may be arranged, as is known in the art, to construct nonvolatile random access memories (NOVRAM's) and electrically erasable programmable read only memories (EEPROM's). See, e.g., U.S. Pat. No. 4,300,212, which discloses a NOVRAM device and U.S. Pat. No. 4,486,769, which discloses an EEPROM device. Of course, the principles of the present invention are applicable to other devices utilizing floating gate technology.
In U.S. Pat. No. 4,274,012, for example, the disclosed nonvolatile memory cell has three layers of polysilicon, each layer being generally electrically isolated from the substrate and each other. The first polysilicon layer is a programming electrode. The second polysilicon layer is the floating gate. The floating gate has a portion capacitively coupled to the programming electrode to form a programming tunneling region in which electrons tunnel from the programming electrode to the floating gate. Another portion of the floating gate is capacitively coupled to a n-implant region in the p-type substrate. The n-implant region is a bias electrode. The third polysilicon layer, which is an erase/store electrode, is capacitively coupled to a portion of the floating gate to form an erase tunneling region in which electrons tunnel from the floating gate to the erase/store electrode. Another portion of the erase/store electrode is capacitively coupled to the bias electrode in the substrate.
To initiate tunneling, a high potential, such as 25 v, is applied to the erase/store electrode while the programming electrode is held at a low potential, such as ground. The substrate bias electrode is caused to be held either at the low potential of the programming electrode or held at the high potential of the erase/store electrode, depending on whether electrons are to be tunneled from or to the floating gate, respectively. With the bias electrode held at the high potential, the floating gate being strongly capacitively coupled to the bias electrode is elevated to the high potential. Therefore, high potential exists across the programming tunneling region between the programming electrode and the floating gate so that electrons are tunneled onto the floating gate. Conversely, with the bias electrode held at the low potential, the floating gate will also be at the low potential because of the strong capacitive coupling to the bias electrode. Therefore, high potential exists across the erase tunneling region between the floating gate and the erase/store electrode. Electrons will then tunnel from the floating gate to the erase/store electrode.
The potential of the bias electrode is controlled by a transistor switch, wherein the bias electrode forms the source of the transistor. The low potential is applied to the drain of the transistor. When the transistor is turned on, the bias electrode will be electrically coupled to the low potential. When the transistor is off, the potential of the bias electrode is allowed to float. Due to the strong capacitive coupling between the erase/store electrode and the bias electrode, the high potential applied to the erase/store electrode will be capacitively coupled to the bias electrode. The bias electrode will then be elevated to the high potential.
It is desirable to increase the number of memory devices which are fabricated from a single wafer to increase the chip yield per wafer and thereby to reduce the cost of each chip. In this regard, the size of each memory cell within the memory device must be reduced. However, such reductions in size do not allow a simple miniaturization of existing memory cells. For example, tolerances between mask levels may be difficult to maintain or the miniaturized design may require minimum channel widths not compatible with existing technology. Miniaturization of the above-described nonvolatile memory cell does not allow the necessary capacitive values and relationships to be maintained for an operational memory device. For example, each of the third semiconductor layer and the second semiconductor layer overlay a portion of the substrate and the immediate lower order semiconductor layer. It is the overlap between layers which establishes the magnitude of capacitive coupling. Also, the capacitive coupling required between the erase/store electrode and the bias electrode significantly affects device operation speeds.
It is also desirable to make as many of the steps of the process forming the memory cell relatively insensitive to critical tolerances, in particular to lithographic variations of dimensional control and layer to layer registration. A cell having many self-aligned features provides a significant benefit with respect to process tolerance.